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january 2009 rev 3 1/27 27 L6227Q dmos dual full bridge driver with pwm current controller features operating supply voltage from 8 to 52 v 2.8 a output peak current (1.4 a dc) r ds(on) 0.73 ? typ. value @ t j = 25 c operating frequency up to 100 khz non dissipative overcurrent protection dual independent constant t off pwm current controllers slow decay synchronous rectification cross conduction protection thermal shutdown under voltage lockout integrated fast free wheeling diodes applications bipolar stepper motor dual or quad dc motor description the L6227Q is a dmos dual full bridge designed for motor control applic ations, realized in bcdmultipower technology, which combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. the device also includes two independent constant off time pwm current controllers that performs the chopping regulation. available in vqfpn32 5 mm x 5 mm package, the L6227Q features a non-dissipative overcurrent protection on the high side power mosfets and thermal shutdown. vfqfpn32 5 mm x 5 mm www.st.com figure 1. block diagram d99in1085a gate logic ocd a ocd b over current detection over current detection gate logic vcp vboot en a in1 a in2 a en b in1 b in2 b vref a v boot 5v 10v vs a v s b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator one shot monostable masking time thermal protection v boot v boot 10v 10v bridge a sense comparator bridge b rc a + - sense b vref b rc b pwm
contents L6227Q 2/27 contents 1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 pwm current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 output current capability and ic power dissipation . . . . . . . . . . . . . . 21 7 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L6227Q electrical data 3/27 1 electrical data 1.1 absolute maximum ratings 1.2 recommended operating conditions table 1. absolute maximum ratings symbol parameter parameter value unit v s supply voltage v sa = v sb = v s 60 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s = 60 v; v sensea = v senseb = gnd 60 v v boot bootstrap peak voltage v sa = v sb = v s v s + 10 v v in ,v en input and enable voltage range -0.3 to +7 v v refa , v refb voltage range at pins v refa and v refb -0.3 to +7 v v rca, v rcb voltage range at pins rc a and rc b -0.3 to +7 v v sensea, v senseb voltage range at pins sense a and sense b -1 to +4 v i s(peak) pulsed supply current (for each v s pin), internally limited by the overcurrent protection v sa = v sb = v s ; t pulse < 1 ms 3.55 a i s rms supply current (for each v s pin) v sa = v sb = v s 1.4 a t stg , t op storage and operating temperature range -40 to 150 c table 2. recommended operating conditions symbol parameter parameter min max unit v s supply voltage v sa = v sb = v s 852v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s ; v sensea = v senseb 52 v v refa , v refb voltage range at pins v refa and v refb -0.1 5 v v sensea, v senseb voltage range at pins sense a and sense b (pulsed t w < t rr ) (dc) -6 -1 6 1 v v i out rms output current 1.4 a t j operating junction temperature -25 +125 c f sw switching frequency 100 khz
electrical data L6227Q 4/27 1.3 thermal data table 3. thermal data symbol parameter value unit r th(ja) thermal resistance j unction-ambient max (1) . 1. mounted on a double-layer fr4 pcb with a dissipating copper surface of 0.5 cm 2 on the top side plus 6 cm 2 ground layer connected through 18 via holes (9 below the ic). 42 c/w
L6227Q pin connection 5/27 2 pin connection figure 2. pin connection (top view) note: 1 the pins 2 to 8 are connected to die pad 2 the die pad must be connected to gnd pin
pin connection L6227Q 6/27 table 4. pin description n pin type function 1, 21 gnd gnd signal ground terminals. 9out1 b power output bridge b output 1. 11 rc b rc pin rc network pin. a parallel rc network connected between this pin and ground sets the current controller off-time of the bridge b. 12 sense b power supply bridge b source pin. this pin must be connected to power ground through a sensing power resistor. 13 in1 b logic input bridge b input 1 14 in2 b logic input bridge b input 2 15 vref b analog input bridge b current controller reference voltage. do not leave this pin open or connect to gnd. 16 en b logic input (1) bridge b enable. low logic level switches off all power mosfets of bridge b. this pin is also connected to the collector of the over current and thermal protection transistor to implement over current protection. if not used, it has to be connected to +5 v through a resistor. 17 vboot supply voltage bootstrap voltage needed for driving the upper power mosfets of both bridge a and bridge b. 19 out2 b power output bridge b output 2. 20 vs b power supply bridge b power supply voltage. it must be connected to the supply voltage together with pin vs a . 22 vs a power supply bridge a power supply voltage. it must be connected to the supply voltage together with pin vs b . 23 out2 a power output bridge a output 2. 24 vcp output charge pump oscillator output. 25 en a logic input (1) bridge a enable. low logic level switches off all power mosfets of bridge a. this pin is also connected to the collector of the over current and thermal protection transistor to implement over current protection. if not used, it has to be connected to +5 v through a resistor. 26 vref a analog input bridge a current controller reference voltage. do not leave this pin open or connect to gnd. 27 in1 a logic input bridge a logic input 1. 28 in2 a logic input bridge a logic input 2. 29 sense a power supply bridge a source pin. this pin must be connected to power ground through a sensing power resistor. 30 rc a rc pin rc network pin. a parallel rc network connected between this pin and ground sets the current controller off-time of the bridge a. 31 out1 a power output bridge a output 1. 1. also connected at the output drain of the over current and thermal protection mo sfet. therefore, it has to be driven putting in series a resistor with a value in the range of 2.2 k ? - 180 k ? , recommended 100 k ? .
L6227Q electrical characteristics 7/27 3 electrical characteristics table 5. electrical characteristics (t a = 25 c, vs = 48 v, unless otherwise specified) symbol parameter test condition min typ max unit v sth(on) turn-on threshold 5.8 6.3 6.8 v v sth(off) turn-off threshold 5 5.5 6 v i s quiescent supply current all bridges off; t j = -25 c to 125 c (1) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side + low-side switch on resistance t j = 25 c 1.47 1.69 ? t j =125 c (1) 2.35 2.7 ? i dss leakage current en = low; out = v s 2ma en = low; out = gnd -0.3 ma source drain diodes v sd forward on voltage i sd = 1.4 a, en = low 1.15 1.3 v t rr reverse recovery time i f = 1.4 a 300 ns t fr forward recovery time 200 ns logic input v il low level logic input voltage -0.3 0.8 v v ih high level logic input voltage 2 7 v i il low level logic input current gnd logic input voltage -10 a i ih high level logic input current 7 v logic input voltage 10 a v th(on) turn-on input threshold 1.8 2.0 v v th(off) turn-off input threshold 0.8 1.3 v v th(hys) input threshold h ysteresis 0.25 0.5 v switching characteristics t d(on)en enable to out turn on delay time (2) i load =1.4 a, resistive load 500 800 ns t d(on)in input to out turn on delay time i load =1.4 a, resistive load (dead time included) 1.9 s t rise output rise time (2) i load =1.4 a, resistive load 40 250 ns t d(off)en enable to out turn off delay time (2) i load =1.4 a, resistive load 500 800 1000 ns t d(off)in input to out turn off delay time i load =1.4 a, resistive load 500 800 1000 ns t fall output fall time (2) i load =1.4 a, resistive load 40 250 ns t dt dead time protection 0.5 1 s f cp charge pump frequency -25 c < t j < 125 c 0.6 1 mhz
electrical characteristics L6227Q 8/27 pwm comparator and monostable i rca, i rcb source current at pins rc a and rc b v rca = v rcb = 2.5 v 3.5 5.5 ma v offset offset voltage on sense comparator v refa, v refb = 0.5 v 5 mv t prop turn off propagation delay (3) 500 ns t blank internal blanking time on sense pins 1 s t on(min) minimum on time 2.5 3 s t off pwm recirculation time r off = 20 k ?; c off = 1 nf 13 s r off = 100 k ?; c off = 1 nf 61 s i bias input bias current at pins vref a and vref b 10 a over current protection i sover input supply overcurrent protection threshold t j = -25 c to 125 c (1) 2.8 a r opdr open drain on resistance i = 4 ma 40 60 ? t ocd(on) ocd turn-on delay time (4) i = 4 ma; c en < 100 pf 200 ns t ocd(off) ocd turn-off delay time (4) i = 4 ma; c en < 100 pf 100 ns 1. tested at 25 c in a restricted r ange and guaranteed by characterization. 2. see figure 3 on page 9 3. measured applying a voltage of 1 v to pin sense and a voltage drop from 2 v to 0 v to pin vref. 4. see figure 4 on page 9 table 5. electrical characteristics (continued) (t a = 25 c, vs = 48 v, unless otherwise specified) symbol parameter test condition min typ max unit
L6227Q electrical characteristics 9/27 figure 3. switching char acteristic definition figure 4. overcurrent de tection timing definition v th(on) v th(off) 90% 10% en i out t t t fall t d(off)en t rise t d(on)en d01in1316 i sover 90% 10% i out v en t ocd(off) t ocd(on) d02in1399 on off bridge
circuit description L6227Q 10/27 4 circuit description 4.1 power stages and charge pump the L6227Q integrates two independent power mos full bridges. each power mos has an r ds(on) = 0.73 ? (typical value @ 25 c), with intr insic fast freewheeling diode. cross conduction protection is achieved using a dead time (td = 1 s typical) between the switch off and switch on of two power mos in one leg of a bridge. using n-channel power mos for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped (vboot) supply is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 5 . the oscillator output (vcp) is a squa re wave at 600 khz (typical) with 10 v amplitude. recommended values/part numbers for the charge pump circuit are shown in table 6 . figure 5. charge pump circuit table 6. charge pump external components values component value c boot 220 nf c p 10 nf d1 1n4148 d2 1n4148 d2 c boo t d1 c p v s vs a vcp vboo t vs b d01in132 8
L6227Q circuit description 11/27 4.2 logic inputs pins in1 a , in2 b , in1 b and in2 b are ttl/cmos and microcontroller compatible logic inputs. the internal structure is shown in figure 6 . typical value for turn-on and turn-off thresholds are respectively vthon = 1.8 v and vthoff = 1.3 v. pins en a and en b have identical input structure with the exception that the drains of the overcurrent and thermal protection mosfets (one for the bridge a and one for the bridge b) are also connected to these pins. due to these connections some care needs to be taken in driving these pins. the en a and en b inputs may be driven in one of two configurations as shown in figure 7 or figure 8 . if driven by an open drain (collector) structure, a pull-up resistor r en and a capacitor c en are connected as shown in figure 7 . if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in figure 8 . the resistor r en should be chosen in the range from 2.2 k ? to 180 k ? . recommended values for r en and c en are respectively 100 k ? and 5.6 nf. more information on selecting the values is found in the overcurrent protection section. figure 6. logic inputs internal structure figure 7. en a and en b pins open collector driving figure 8. en a and en b pins push-pull driving 5v d01in1329 esd protection 5v 5v open collector output r en c en en d01in133 0 esd protection 5v push-pull output r en c en en d01in1331 esd protection
circuit description L6227Q 12/27 4.3 truth table 4.4 pwm current control the L6227Q includes a constant off time pwm current controller for each of the two bridges. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power mos transistors and ground, as shown in figure 9 . as the current in the load builds up the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor becomes greater than the voltage at the reference input (vref a or vref b ) the sense comparator triggers the monostable switching the low-side mos off. the low-side mos remain off for the time set by the monostable and the motor current recirculates in the upper path. when th e monostable times out the bridge will again turn on. since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power mos, the effective off time is the sum of the monostable time plus the dead time. figure 9. pwm current controller simplified schematic table 7. truth table inputs outputs description (1) 1. valid only in case of load connected between out1 and out2 en in1 in2 out1 out2 lx (2) 2. x = don't care x high z (3) 3. high z = high impedance output high z disable h l l gnd gnd brake mode (lower path) h h l vs gnd (vs) forward h l h gnd (vs) (4) 4. gnd (vs) = gnd during ton, vs during toff vs reverse h h h vs vs brake mode (upper path)
L6227Q circuit description 13/27 figure 10 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the rc pin voltage and the status of the bridge. immediately after the low-side power mos turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. the L6227Q provides a 1 s blanking time t blank that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable. figure 10. output current regulation waveforms figure 11 shows the magnitude of the off time t off versus c off and r off values. it can be approximately calculated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally generated dead time with: 20 k ? r off 100 k ? 0.47 nf c off 100 nf t dt = 1 s (typical value) therefore: t off(min) = 6.6 s t off(max) = 6 ms off bc dd a t on t off t off bc on 2.5v 0 fast decay fast decay slow decay slow decay 1 s t blank t rcrise 1 s t dt 1 s t dt t rcrise t rcfall t rcfall synchronous or quasi synchronous rectification 1 s t blank 5v v rc v sense v ref i out v ref r sense d01in1334
circuit description L6227Q 14/27 these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin r coff . the rise time t rcrise will only be an issue if the capacitor is no t completely charged before the next time the monostable is triggered. therefore, the on time t on , which depends by motors and supply parameters, has to be bigger than t rcrise for allowing a good current regulation by the pwm stage. furthermore, the on time t on can not be smaller than the minimum on time t on(min) . t rcrise = 600 c off figure 12 on page 15 shows the lower limit for the on time t on for having a good pwm current regulation capacity. it has to be said that t on is always bigger than t on(min) because the device imposes this condition, but it can be smaller than t rcrise - t dt . in this last case the device continues to work but the off time t off is not more constant. so, small c off value gives more flexibility for the app lications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for c off , the more influential will be the noises on the circuit performance. figure 11. t off versus c off and r off t on t on min () > 2.5 s = t on t tcrise t dt ? w + > ? ? ? 0.1 1 10 100 1 10 100 1 . 10 3 1 . 10 4 coff [nf] toff [ s] r off = 100k ? r off = 47k ? r off = 20k ?
L6227Q circuit description 15/27 figure 12. area where t on can vary maintaining the pwm regulation 4.5 slow decay mode figure 13 shows the operation of the bridge in the slow decay mode. at the start of the off time, the lower power mos is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slowly. after the dead time the upper power mos is operated in the synchronous rectification mode. when the monostable times out, the lower power mos is turned on again after some delay set by the dead time to prevent cross conduction. figure 13. slow decay mode output stage configurations 0.1 1 10 100 1 10 100 coff [nf] ton(min) [ s] 1.5 s (typ. value)
circuit description L6227Q 16/27 4.6 non-dissipative overcurrent protection the L6227Q integrates an overcurrent detection circuit (ocd). this circuit provides protection against a short circuit to ground or between two phases of the bridge. with this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. figure 14 shows a simplified schematic of the overcurrent detection circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference current i ref . when the output current in one bridge reaches the detection threshold (typically 2.8 a) the relative ocd comparator signals a fault condition. when a fault condition is detected, the en pin is pulled below the turn off threshold (1.3 v typical) by an internal open drain mos with a pull down capability of 4 ma. by using an extern al r-c on the en pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. figure 14. overcurrent protection simplified schematic figure 15 shows the overcurrent detection operation. the disable time t disable before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. it is affected whether by c en and r en values and its magnitude is reported in figure 16 . the delay time t delay before turning off the bridge when an overcurrent has been detected depends only by c en value. its magnitude is reported in figure 17 . c en is also used for providing immunity to pin en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2 k ? to 180 k ? . recommended values for r en and c en are respectively 100 k ? and 5.6 nf that allow obtaining 200 s disable time. + over temperature i ref (i 1a +i 2a ) / n i 1a / n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out1 a out2 a vs a i 1a i 2a i 2a / n from the bridge b ocd comparator ocd comparator to gate logic internal open-drain r ds(on) 40 ? typ. c en . r en .en v dd c or logic d01in1337
L6227Q circuit description 17/27 figure 15. overcurrent protection waveforms figure 16. t disable versus c en and r en (v dd = 5 v) i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en v en bridge on off ocd on off d02in1400 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k ? r en = 100 k ? r en = 47 k ? r en = 33 k ? r en = 10 k ? 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k ? r en = 100 k ? r en = 47 k ? r en = 33 k ? r en = 10 k ?
circuit description L6227Q 18/27 figure 17. t delay versus c en (v dd = 5 v) 4.7 thermal protection in addition to the ovecurrent protection, the L6227Q integrates a thermal protection for preventing the device destruction in case of junction over temperature. it works sensing the die temperature by means of a sensible element integrated in the die. the device switch-off when the junction temperature reaches 165 c (typ. value) with 15 c hysteresis (typ. value). 110100 0.1 1 10 cen [nf] tdelay [ s]
L6227Q application information 19/27 5 application information a typical application using L6227Q is shown in figure 18 . typical component values for the application are shown in table 8 . a high quality ceramic capacitor in the range of 100 to 200 nf should be placed between the power pins (vs a and vs b ) and ground near the L6227Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitors connected from the en a and en b inputs to ground set the shut down time for the bridge a and bridge b respectively when an over current is detected (see overcurrent protection). the two current sensing inputs (sense a and sense b ) should be connected to the sensing resistors with a trace length as short as possible in the layout. the sense resistors should be non-inductive resistors to minimize the di/dt transients acro ss the resistor. to increase noise immunity, unused logic pins (except en a and en b ) are best connected to 5 v (high logic level) or gnd (low logic level) (see pin description). it is recommended to keep power ground and signal ground separated on pcb. table 8. component values for typical application component value c 1 100 f c 2 100 nf c a 1 nf c b 1 nf c boot 220 nf c p 10 nf c ena 5.6 nf c enb 5.6 nf c refa 68 nf c refb 68 nf d 1 1n4148 d 2 1n4148 r a 39 k ? r b 39 k ? r ena 100 k ? r enb 100 k ? r sensea 0.6 ? r senseb 0.6 ?
application information L6227Q 20/27 figure 18. typical application note: to reduce the ic thermal resistance, therefore improve the dissipation path, the nc pins can be connected to gnd.
L6227Q output current capability and ic power dissipation 21/27 6 output current capability and ic power dissipation in figure 19 and figure 20 are shown the approximate relation between the output current and the ic power dissipation using pwm current control driving two loads, for two different driving types: ? one full bridge on at a time ( figure 19 ) in which only one load at a time is energized. ? two full bridges on at the same time ( figure 20 ) in which two loads at the same time are energized. for a given output current and driving type the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 c maximum). figure 19. ic power dissipation vs output current with one full bridge on at a time figure 20. ic power dissipation versus output current with two full bridges on at the same time no pwm f sw = 3 0 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out one full bridge on at a time p d [w] i out [a] 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10 no pwm f sw = 30 khz (slow decay) test conditions: supply volt age = 24 v i a i b i out i out p d [w ] i out [a ] two full bridges on at the same time 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10
thermal management L6227Q 22/27 7 thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides the available space on the pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. for instance, using a vfqfpn32l 5x5 package the typical rth(ja) is about 42 c/w when mounted on a double-layer fr4 pcb with a dissipating copper surface of 0.5 cm 2 on the top side plus 6 cm 2 ground layer connected through 18 via holes (9 below the ic).
L6227Q package mechanical data 23/27 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. note: 1 vfqfpn stands for thermally enhanced very thin profile fine pitch quad flat package no lead. very thin profile: 0.80 < a = 1.00 mm. 2 details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features. table 9. vfqfpn32 5x5x1.0 pitch 0.50 dim. databook (mm) min typ max a 0.80 0.85 0.95 b 0.18 0.25 0.30 b1 0.165 0.175 0.185 d 4.85 5.00 5.15 d2 3.00 3.10 3.20 d3 1.10 1.20 1.30 e 4.85 5.00 5.15 e2 4.20 4.30 4.40 e3 0.60 0.70 0.80 e0.50 l 0.30 0.40 0.50 ddd 0.08
package mechanical data L6227Q 24/27 figure 21. package dimensions
L6227Q order codes 25/27 9 order codes table 10. order code order code package packaging L6227Q vfqfpn32 5 x 5 x 1.0 mm tube
revision history L6227Q 26/27 10 revision history table 11. document revision history date revision changes 07-dec-2007 1 first release 10-jun-2008 2 updated: figure 18 on page 20 added: note 1 on page 4 28-jan-2009 3 updated value in table 3: thermal data on page 4
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